#sccs	"@(#)uts/kern/sys:hardware.m	1.1"

 #	Convergent Technologies - System V - Jul 1983

#ifndef hardware_m
#define hardware_m
 #S4 HARDWARE DEFINITION - processor
 #	68010 ASSEMBLY INCLUDE FILE
 #	(see also iohw.m for peripherals)
 #
 #	FILE NAME: hardware.m
 #

 #Memory mapping hardware
 #from sys/param.h
set	VUSER_START,0x80000	# start address of user process
set	VUSER_END,0x300000	# end address of user process
set	SHLIB_START,VUSER_END
set	SHLIB_END,0x380000
set	KVMEM_START,SHLIB_END
set	KVMEM_END,0x400000
set	MAXUMEM,0x300
set	SYSPAGE,0x80

set	KVMEM_PAGES,128
set	SHLIB_PAGES,128

set	PG_BASE,0x400000	#address of page table
set	USER_MAP,PG_BASE + 256	# address of user part of page table
set	MAP_TOP,PG_BASE+2048-512 # address past end of user memory map
set	SL_MAP,MAP_TOP		# address of shlib part of page table
set	KV_MAP,MAP_TOP+256	# address of kvmem part of page table
set	UPTE,0x4000E0		# address of UPAGE pte

 #Page table entry.
 #WE	 bit 15		=1 user can write page, =0 user can read page
 #USE	 bits 14-13	value 0=not present, 1=present, not accessed
 #			value 2=accessed not written, 3=written to
 #PAGEADDR bits 8-0	PHYSADDR=(PAGEADDR*4096) + byte within page
 #STATES:
 #page not in memory:	WE set as needed and rest=0
 #page in memory:	WE, PAGEADDR set as needed and USE non zero

set	PROT_MASK,0x8000	#mask for write bit
set	USE_MASK,0x6000		#mask for usage bits
set	PG_MASK,0x3ff		#page address mask
set	PG_WRITE,0x8000		#user write enable
set	NO_PAGE,0x0		#to initialize pte's
set	PG_IN,0x7fff		#AND mask
set	PG_PRESENT,0x2000	#pte&USE_MASK page just in 
set	PG_NOT_DIRTY,0x4000	#pte&USE_MASK=accessed 
set	PAGE_DIRTY,0x6000	#pte&USE_MASK=written to
set	P_ACCESS_CHECK,0x6000	#AND mask
set	NO_ACCESS,0


set	TOTAL_PTES,1024
set	TOTAL_PAGES,1024
set	PAGES_IN_PROC,1024-KVMEM_PAGES-SHLIB_PAGES
set	BYTES_PER_PAGE,0x1000
set	PAGESHIFT,12		#gets page number from addr

 #4 Mbyte logical address space
set	MAX_MEM,0x400000
 #4 Mbyte physical address space
set	MAX_PHYS_MEM,0x400000

set	PAGES_PER_SEG,16	#needed to correspond to megaframe rounding

 #some defines that lie about some things
set	SEGS_PER_PROC,64	#miniframe doesn't have segments
set	SEGSHIFT,4		#seg to page
set	PG_KR,0			#the kernel can read anything
set	PG_KW,0			#the kernel can write to anything

 #Page table entry masks
set	PG_PROT,0x00008000
set	PG_STAT,0x00006000
set	PG_ACC,0x00004000
set	PG_V,0x00002000
set	PG_M,0x00006000
set	PG_FOD,0x00001000
set	PG_VREADM,0x00000400
set	PG_PFNUM,0x000003ff

set	USIZE,1		#number of pages in usrtbl (upage)
set	USRSIZE,4096	#size of usrtbl (upage) in bytes
set	SEGSIZE,0x10000	#size of a segment

 #processor (mostly) registers
 #from sys/hardware.h

 #WARNING:	All these definitions are set up on the assumption
 #that they are operating on 16 bit quantities read/written from/to
 #the even address specified as the register address.
 #It is further assumed that all reads/writes of hardware registers
 #will be performed as 16 bit transfers to the even byte address.
 #It is believed that other schemes may work, but this is the way
 #these definitions are set up.

 #68010 status bits
set	S_TRACE,0x8000
set	S_SUPV,0x2000
set	S_INTMASK,0x700
set	HIGH,S_SUPV + S_INTMASK	#high priority supervisor mode (spl 7)
set	LOW,S_SUPV		#low priority, supervisor mode (spl 0)

 #General Control Register - GCR	
 #Write only.	Uses address bits 16-18 of I/O address E4X000

set	SYSERR_GCR_ADDR,0xE40000	#EE+
set	SYSERR_ENABLE,0x8000		#EE	1=enable NMI/BERR
set	SYSERR_DISABLE,0x0000		#EE	0=enable NMI/BERR

set	PE_INT_GCR_ADDR,0xE41000	#PIE+
set	PE_INT_ENABLE,0x8000		#PIE	1=enable PE's
set	PE_INT_DISABLE,0x0000		#PIE	1=disable PE's

set	PE_FRC_GCR_ADDR,0xE42000	#BP+
set	PE_FRC_ENABLE,0x8000		#BP	1=force bad parity
set	PE_FRC_DISABLE,0x0000		#BP	1=force bad parity

set	ROM_GCR_ADDR,0xE43000		#ROMLMAP-
set	ROM_DISABLE,0x8000		#ROMLMAP 1=ROM disabled at low addr
set	ROM_ENABLE,0x0000		#ROMLMAP 0=ROM mapped at low addr

set	L1MD_GCR_ADDR,0xE44000		#L1MD-
set	L2MD_GCR_ADDR,0xE45000		#L2MD-
set	MD_DISCONNECT,0x8000		#L1MD	modem disconnected from line 
set	MD_CONNECT,0x0000		#L1MD	modem connected to line 


set	DNCT1_GCR_ADDR,0xE46000		#D/NCD1-
set	DNLN2_CONNECT,0x8000		#D/NCD1	1 = dial/network connected 
					#	to line 2
set	DNLN1_CONNECT,0x0000		#D/NCD1	0 = dial/network connected 
					#	to line 1

 #	Miscellaneous Control Register - MCR (4A0,000) (w)
 #	Write only.	Uses most significant byte of 16 bit word

set	MCR_ADDR,0x4a0000
set	CLRSINT,0x8000		#CLRSINT- toggle from 1 to 0 and back to
				#	1 to dismiss level 6, 60 hertz
				#	interrupt
set	DMA_READ,0x4000		#DMAR/W- 0 = disk DMA write
				#	 1 = disk DMA read
set	LPSTB,0x2000		#LPSTB+  toggle from 0 to 1 and back
				#	to 0 to strobe data to line printer
set	MCKSEL,0x1000		#MCKSEL- 0 = modem RX & TX selected
				#	 1 = programmable Baud Rate
				#		generator is selected
set	LED3,0x800		#LED3-	 0 = on, 1 = off
set	LED2,0x400		#LED2-	 0 = on, 1 = off
set	LED1,0x200		#LED1-	 0 = on, 1 = off
set	LED0,0x100		#LED0-	 0 = on, 1 = off

 #General Status Register - GSR (410,000) (r)
 #Read only.	Uses most significant byte of 16 bit word

set	GSR_ADDR,0x410000
set	R_W_CYCLE,0x4000	#R/W-	1=read cycle
set	NPC_CYCLE,0x2000	#NPC+	1=DMA 0=processor
set	PAGE_FAULT,0x1000	#PF-	0=page fault
set	PIE_STATE,0x400		#PIE+	1=PE's are enabled
set	USR_IO_FAULT,0x100		#UIE-	0=user accessed I/O

 #Clear Status Register - CSR
 #Read/Write.	Uses most significant byte of 16 bit word
 #Any access to this register clears the GSR and BSR0, BSR1

set	CSR_ADDR,0x4C0000

 #Bus Status Register 0 - BSR0 (430,000) (r)
 #Read only.	Uses 16 bit word
 #Latched at the same time as the GSR and BSR1, also cleared by CSR

set	BSR0_ADDR,0x430000
set	MMU_ERR,0x8000		# 0=mmu error:
				#	processor or DMA page fault
				#	user writing to write protected page
				#	user accessing kernel space
set	NOT_DGNT,0x4000		#DKBG-	 0 = disk DMA cycle
set	NOT_XGT0,0x2000		#EXP0BG- 0 = EXP0 DMA cycle
set	NOT_XGT1,0x1000		#EXP1BG- 0 = EXP1 DMA cycle
set	NOT_XGT2,0x800		#EXP2BG- 0 = EXP2 DMA cycle
set	NOT_XGT3,0x400		#EXP3BG- 0 = EXP3 DMA cycle
set	UPPER_DATA_STROBE,0x200	#UDS-    0 = Upper Data Strobe from 68010
set	LOWER_DATA_STROBE,0x100	#LDS-    0 = Lower Data Strobe from 68010
set	PA23,0x80		#PA23	 Processor Address 23
set	PA22,0x40		#PA22	 Processor Address 22
set	LA21,0x20		#A21	 Logical Address 21
set	LA20,0x10		#A20	 Logical Address 20
set	LA19,0x8 		#A19	 Logical Address 19
set	LA18,0x4 		#A18	 Logical Address 18
set	LA17,0x2 		#A17	 Logical Address 17
set	LA16,0x1 		#A16	 Logical Address 16
set	A23_A16_MASK,0xff	#mask of A23 to A16
set	A21_A16_MASK,0x3f	#mask of A21 to A16

 #Bus Status Register 1 - BSR1
 #Read only.	Uses all of 16 bit word
 #Latched at the same time as the GSR and BSR0, also cleared by CSR

set	BSR1_ADDR,0x440000
set	A15_A00_MASK,0xffff	#mask of A15 to A0

 #	Hardware Register Definitions

set	KSTACK,0x70900		#kernel stack address
set	PG_USER,0x70		#virtual page no of user table

 #	mcr_save must be written to whenever the real MCR is written to.
 #		global	mcr_save

 #	address in vector table of a pointer to the CDT.
set	pCDT,0x3F8		#software leaves pointer in penultimate int vector

 #	CDT signature long word
set	SIG1,0x45504A52

 #		Format - to be used by crash in analyzing dump
 #
 #			0000 - 003F:	machine registers
 #			0040 - 0041:	GSR
 #			0042		set to zero
 #			0043 - 0045:	BSR
 #			0046 - 0845	memory map registers
 #			0846 - 08C5	CDT

 #	Displacements from the start of a crash dump plus SAVEAREA.
set	SAVEAREA,0x0000
set	SVREGS,0x0000
set	SVGSR,0x0040
set	SVBSR,0x0042
set	SVMAP,0x0046
set	SVCDT,0x0846

 #		Format of the CDT (128 bytes)
 #		signature		4 bytes
 #		lbolt			4 bytes
 #		time of day		4 bytes
 #		reason			1 byte
 #		(0 = panic, 1 = reset, 2 = poweron)
 #		boot media		1 byte
 #		(2 = fd, 1 = syq, 0 = hd)
 #		panic string		114 bytes
set	CdtSig,0x00
set	CdtLbolt,0x04
set	CdtTOD,0x08
set	CdtReason,0x0C
set	CdtMedia,0x0D
set	CdtPanic,0x0E
set	SZPANIC,114
set	SZCDT,128

 #	Disk types.
set	HD,0		#Winchester
set	SY,1		#syquest
set	FD,2		#Floppy

 #	Reasons
set	PANIC,0
set	RESET,1
set	POWERON,2

 #	copy of VHBMAGIC from gdisk.h
set	VHBMAGIC,0x55515651

 #	Address the loader is loaded at
set	LOADADDR,0x70000
set	BOOTCDT,LOADADDR-SZCDT

#endif hardware_m
