#sccs	"@(#)uts/kern/sys:iohw.m	1.1"

 #	Convergent Technologies - System V - Jul 1983

#ifndef iohw_m
#define iohw_m
 # S4 HARDWARE DEFINITION - peripherals
 #	68010 ASSEMBLY INCLUDE FILE
 #	(see also hardware.h for processor)
 #
 #	FILE NAME: iohw.m
 #

 #	value to use in writing to io control registers to trigger actions.
set	ACTIVATE,0


 #RS-232 Ports A + B Registers  - 8274-A
 #Port A is used for RS-232, port B is not used
 #	except for detecting events.
 #Uses the least significant byte of 16 bit word

set	A_DATA_ADDR,0xE50000	#R/W
set	B_DATA_ADDR,0xE50002	#R/W
set	A_CMND_ADDR,0xE50004	#WO
set	B_CMND_ADDR,0xE50006	#WO


 #RS-232 Ports C + D Registers  - 8274-B
 #Uses the least significant byte of 16 bit word

set	C_CMND_ADDR,0xE70000	#WO
set	C_DATA_ADDR,0xE70002	#R/W


 #Parallel Line Printer Registers
 #Uses the least significant byte of 16 bit word

set	LP_STATUS_ADDR,0x470000	#R
set	LP_DATA_ADDR,0x4F0000	#W
 #bits in the status register on reading
set	LP_BUSY,0x80		#LPB+	  1 = lp busy
set	LP_SELECTED,0x40	#LPS+	  1 = lp selected
set	LP_OUT_PAPER,0x20	#NP+	  1 = lp out of paper
set	LP_ERR,0x10		#LPERR-	  0 = lp error
set	FDINTRQ,0x08		#FDINTRQ+ 1 = floppy interrupt
set	HDINTRQ,0x04		#HDINTRQ+ 1 = hard disk interrupt
set	PARITY_ERR,0x02		#PERR-	  0 = parity error
set	DTDET,0x01		#DTDET-	  0 = dial tone detected

 #DISK Bus interface registers
 #Uses the least significant byte of 16 bit word

set	HD_BASE,0xE00000
set	FD_BASE,0xE10000

set	DMA_CNT,0x460000		#R/W
set	DMA_LOADDR_ADDR,0x4D0000	#W
set	DMA_HIADDR_ADDR,0x4D0100	#W

set	DISK_CNTRL_ADDR,0x4E0000	#R/W
set	MCR_ADDR,0x4A0000		#W

 #Bits in Disk Control Register

set	NOT_FDRST,0x80		#0 = reset, 1 = not reset
set	FDR0,0x40		#1 = floppy selected
set	FDMTR,0x20		#1 = floppy motor on
set	NOT_HDRST,0x10		#0 = hdc reset, 1 = hdc not reset
set	HDR0,0x08		#1 = hard disk 0 selected
set	HDSEL,0x07		#Head select mask

 #Note: Bit 7 of the general control register is used as hard disk 1
 #select in machines with this hardware modification.  This is an otherwise
 #unused, bit-addressable bit at address 4c7000

 #Also note: All bits of the disk control register will be 0 after reset

 #Bits in the miscellaneous control registers pertaining to dma

 #set	DMA_READ,0x4000	|0 = dma write, 1 = dma read

 #Bits in dma count register

set	DMA_ENABLE,0x8000	#0 = dma disable, 1 = dma enabled
set	DMA_CNT_MASK,0x3fff	#Bits 13...0 holds dma count
set	DMA_ERROR,0x8000	#dma error bit mask, 0 = error

 #Bits in line printer status register pertaining to disk driver

 #set	FDINTRQ,0x08		#1 = fdc interrupt
 #set	HDINTRQ,0x04		#1 = hdc interrupt

 #Masks for dma addresses

set	DMA_LO_MASK,0x01fe
set	DMA_HI_MASK,0x3ffe

#endif iohw_m
