Pin Freeze File:  version M1.5.19

;If you have made significant changes to your 7300 design and have trouble
;recreating the same pinout try disabling the FREEZE_OPTIMIZATION option.

;Removing the semicolon on the FREEZE_OPTIMIZATION line below disables this
;option.  FREEZE_OPTIMIZATION=OFF tells the optimization software to
;take account of the pin-assignments (e.g., apply different collapsing
;rules to logic assigned to fast-function blocks).
;Do NOT use this option when targeting a 9500 device.
;FREEZE_OPTIMIZATION: OFF
957284 XC9572-15-PC84
clk7d5 S:PIN9
ecp_mode S:PIN44
host_ack S:PIN17
host_clk S:PIN53
rev_req S:PIN5
pdata0 S:PIN11
pdata1 S:PIN83
pdata2 S:PIN21
pdata3 S:PIN69
pdata4 S:PIN33
pdata5 S:PIN68
pdata6 S:PIN46
pdata7 S:PIN71
relay0 S:PIN55
relay1 S:PIN57
relay2 S:PIN61
relay3 S:PIN13
relay4 S:PIN20
relay5 S:PIN23
relay6 S:PIN4
relay7 S:PIN62
ack_rev S:PIN52
our_addr S:PIN7
periph_ack S:PIN37
periph_clk S:PIN19
periph_req S:PIN72
rev_req_cnt0 S:PIN75
rev_req_cnt1 S:PIN79
rev_req_sync S:PIN81
xflag S:PIN41


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_1 relay6
PARTITION FB1_4 our_addr par_rx_rising_Q reg_num2_Q pdata0 reg_num1_Q
                    reg_num0_Q relay3 host_clk_d1_Q data_mode_Q
                    relay4 byte_cnt1_Q byte_cnt0_Q relay5
                    host_clk_cnt1_Q host_clk_cnt0_Q

PARTITION FB2_2 pdata3
PARTITION FB2_4 pdata5
PARTITION FB2_6 pdata7
PARTITION FB2_8 periph_req
PARTITION FB2_10 rev_req_cnt0
PARTITION FB2_12 rev_req_cnt1
PARTITION FB2_14 rev_req_sync pdata1

PARTITION FB3_5 periph_clk
PARTITION FB3_8 pdata2
PARTITION FB3_11 pdata4 xflag
PARTITION FB3_15 periph_ack

PARTITION FB4_1 pdata6
PARTITION FB4_4 ack_rev
PARTITION FB4_7 relay0
PARTITION FB4_10 relay1
PARTITION FB4_13 relay2
PARTITION FB4_16 relay7
PARTITION FB4_18 host_clk_d2_Q