*1000


RAMSTR,	TLS	/INITIALISIERUNG
	CLA
	TAD RAM10
	CIA
	DCA RAMRDC
	DCA RAMERL
	DCA RAMERH
	DCA RAMADR

	RCHAR	/	UEBERSCHRIFT
	CHECK
	304
	JMP RAMIN
	JMP RAMCOM

RAMCOM,	LINE
	LINE
	TDC
	4322
	4301
	4315
	4240
	4316
	4322
	4272
	240
RAMSPE,	RTCHAR
	CHECK
	212	/END OF COMMENT
	JMP RAMIN
	JMP RAMSPE

RAMIN,	LINE
	TDC
	4304
	4301
	4324
	4301
	240


	JMP INTRPT

	LINE

INONE,	RTCHAR
	CLA
	TAD RAMSZL	/TEST FUER EINZULESENDES BIT
	DCA RAMVGL
	TAD BITIN1
	MQL
	JMP BITINI


INZERO,	RTCHAR
	CLA
	TAD RAMSNL	/TEST FUER EINZULSESENDES BIT
	DCA RAMVGL
	TAD BITIN0
	MQL

BITINI,	CMA	/CLEAR SELECT. OUTPUT REG. OUTPUT=HIGH
	6515
	CLA

RAMWR,	TAD RAMADR
	CMA
	6506	/CLEAR SELECT. OUTPUT REG. 0
	CMA
	6505

	SWP
	6516	/SET RESPECTIVE OUTPUT REG.  OUTPUT=0
	BSW
	6515
	BSW
	MQL
	TAD RAMADR
	CIA
	TAD RMSIZE
	SNA CLA
	JMP .+3

	ISZ RAMADR
	JMP RAMWR

	TAD BITOUT
	MQL
RAMRDN,	DCA RAMADR

RAMRD,	TAD RAMADR
	CMA
	6506
	CMA
	6505
	MQA CLA
	6516	/SET SELECTIVE OUTPUT REG (MQ V ACC)
	6514	/EINLESEN;DIE VERSCHIEDENEN AUSGANGSSIGN.
	RAL CLL	/KOMMEN ALS HIHG AN
	MQA CLA
	6515	/CLEAR SELECTIVE OUTPUT REG.

RAMVGL,	SZL	/WIRD GEAENDERT JE NACH EINLESEN VON 0 ODER 1
	JMP .+4
	ISZ RAMERL
	SKP
	ISZ RAMERH

	CLA
	TAD RAMADR
	CIA
	TAD RMSIZE
	SNA CLA
	JMP RMEND

	ISZ RAMADR
	JMP RAMRD

RMEND,	ISZ RAMRDC
	JMP RAMRDN
	JMP I .+1
	RAMERR



RAM10,	12
RAMRDC,	0
RAMERL,	0
RAMERH,	0
RAMSNL,	7420
RAMSZL,	7430
BITIN0,	5474
BITIN1,	7454
BITOUT,	44
RAMADR,	0
RMSIZE,	1777


PAGE



RAMERR,	LINE
	TDC
	4306
	4305
	4310
	4314
	4305
	4322
	240
	TAD RAMERH
	TOCT
	TAD RAMERL
	TOCT
	LINE
	LINE
	JMP RAMSTR






INTRPT,	KSF
	JMP .-1
	KRS
	CHECK
	260
	JMP INZERO
	CHECK
	261
	JMP INONE
	MOSTSR
	CLA
	JMP RAMSTR