/SUBROUTINEN ZUM TESTEN VON RAMS /******************************** STROBE=4000 PDP8CF=100 PDP8WR=40 PDP8WL=20 INTRPT=4 RESET=1 HOLD=2 HIGH=400 LOW=200 SELECT=3400 MEMADR=0 DEVADR=0 MEMDAT=1000 PDPDAT=3000 FORMAT=2200 STATUS=3200 CLOCK=2400 DATOUT=2000 FIELD 0 *50 RMTSTS RAMLOD RAMRED RAMCEK RMFLSR FIELD 2 *40 SRCLR SRSET SRPULN SRINPT SROUT SRLOAD SRREAD STOC16 RMTSTS RAMLOD RAMRED RAMCEK RMFLSR FRMPDP, 257 FRMHPR, 0 SRPULP PROGTM, 0 SRINIT CLEAR=JMS I 40 SET=JMS I 41 NPULSE=JMS I 42 INPUT=JMS I 43 OUTPUT=JMS I 44 LOAD=JMS I 45 READ=JMS I 46 TOCT16=JMS I 47 RMTEST=JMS I 50 RMLOAD=JMS I 51 RMREAD=JMS I 52 RMCHEK=JMS I 53 RAMFIL=JMS I 54 PPULSE=JMS I 57 INIT=JMS I 61 *600 /CALL RAMLOD LADEN VON DATEN AUS PDP8 IN TESTER-MEMORY /1. ARGUMENT: ANFANGSADR. LOW TESTER-MEMORY 8 BIT /2. ARGUMENT: ANFANGSADR. HIGH TESTER-MEMORY 8 BIR /3. ARGUMENT: ENDADR. LOW TESTER-MEMORY 8 BIT /4. ARGUMENT: ENDADR.: HIGH TESTER-MEMORY 8 BIT /5. ARGUMENT: ANFANGSADR. LOW PDP8 12 BIT /6. ARGUMENT: ANFANGSADR. HIGH PDP8 3 BIT RAMLOD, 0 CAM RDF TAD N6203A DCA RETIN1 SWAB TAD I RAMLOD ISZ RAMLOD DCA RADEBT TAD I RAMLOD ISZ RAMLOD DCA RADEBT+1 /RAM DESTINATION BOT TAD I RAMLOD ISZ RAMLOD DCA RADETP TAD I RAMLOD ISZ RAMLOD DCA RADETP+1 /RAM DESTINATION TOP TAD I RAMLOD ISZ RAMLOD DCA RASRLO /PDP8 SOURCE LOW TAD I RAMLOD ISZ RAMLOD CDF 20 AND N0003 RAL CLL RTL TAD RASRHI /PDP8 SOURCE HIGH DCA RACDF1 TAD RACDF1 DCA RACDF2 TAD FRMPDP LOAD FORMAT SET PDP8WL PDP8CF PDP8WR STROBE LODLOP, TAD RADEBT LOAD LOW MEMADR TAD RADEBT+1 LOAD HIGH MEMADR RACDF1, 0 TAD I RASRLO CDF 20 LOAD LOW MEMDAT ISZ RASRLO RACDF2, 0 TAD I RASRLO /CLA WENN 8 BIT STELLIGE DATEN CDF 20 LOAD HIGH MEMDAT ISZ RASRLO /NOP WENN 8 STELLIGE DATEN NPULSE PDP8WR CAM DAD RADEBT DCM DAD RADETP DPSZ SKP JMP LODEND ISZ RADEBT CLA TAD RADEBT AND (400 SNA CLA JMP .+3 ISZ RADEBT+1 DCA RADEBT JMP LODLOP LODEND, TAD FRMHPR LOAD FORMAT CLEAR PDP8WL RETIN1, HLT JMP I RAMLOD RADEBT, 0;0 RADETP, 0;0 RASRLO, 0 RASRHI, 6201 N0003, 3 N6203A, 6203 PAGE /CALL RAMRED EINLESEN TESTER-MEMORY DATEN IN PDP8 /1. ARGUMENT: ANFANGSADR. LOW TESTER-MEMORY 8 BIT /2. ARGUMENT: ANFANGSADR. HIGH TESTER-MEMORY 8 BIT /3. ARGUMENT: ENDADR. LOW TESTER-MEMORY 8 BIT /4. ARGUMENT: ENDADR. HIGH TESTER-MEMORY 8 BIT /5. ARGUMENT: ANFANGSADR. LOW PDP8 12 BIT /6. ARGUMENT: ANFANGSADR. HIGH PDP8 3 BIT RAMRED, 0 CAM RDF TAD N6203B DCA RETIN2 TAD I RAMRED ISZ RAMRED DCA RMSRBT TAD I RAMRED ISZ RAMRED DCA RMSRBT+1 /RAM SOURCE BOT TAD I RAMRED ISZ RAMRED DCA RMSRTP TAD I RAMRED ISZ RAMRED DCA RMSRTP+1 /RAM SOURCE TOP TAD I RAMRED ISZ RAMRED DCA RMDELO /PDP8 DESTINATION LOW TAD I RAMRED ISZ RAMRED CDF 20 AND N0003 RAL CLL RTL TAD RMDEHI /PDP8 DESTINATION HIGH DCA RMCDF3 TAD RMCDF3 DCA RMCDF4 TAD FRMPDP LOAD FORMAT SET PDP8WL PDP8CF PDP8WR STROBE READLP, TAD RMSRBT LOAD LOW MEMADR TAD RMSRBT+1 LOAD HIGH MEMADR READ LOW MEMDAT RMCDF3, 0 DCA I RMDELO CDF 20 ISZ RMDELO READ HIGH MEMDAT RMCDF4, 0 CLA /DCA I RMDELO FUER 16 BIT CDF 20 NOP /ISZ RMDELO FUER 16 BIT CAM DAD RMSRBT DCM DAD RMSRTP DPSZ SKP JMP REDEND ISZ RMSRBT CLA TAD RMSRBT AND (400 SNA CLA JMP .+3 ISZ RMSRBT+1 DCA RMSRBT JMP READLP REDEND, TAD FRMHPR LOAD FORMAT CLEAR PDP8WL RETIN2, HLT JMP I RAMRED RMSRBT, 0;0 RMSRTP, 0;0 RMDELO, 0 RMDEHI, 6201 N6203B, 6203 PAGE /CALL RAMCEK PRUEFEN UND BEI GLEICHHEIT SKIP /1. ARGUMENT: ANFANGSADR. LOW TESTER-MEMORY 8 BIT /2. ARGUMENT: ANFANGSADR. HIGH TESTER MEMORY 8 BIT /3. ARGUMENT: ENDADR. LOW TESTER-MEMORY 8 BIT /4. ARGUMENT: ENDADR. HIGH TESTER MEMORY 8 BIT /5. ARGUMENT: ANFANGSADR. LOW PDP8 12 BIT /6. ARGUMENT: ANFANGSADR. HIGH PDP8 3 BIT /7. ARGUMENT: ARGUMENT FUER UNGLEICH RAMCEK, 0 CAM RDF TAD N6203C DCA RETIN3 DCA RMFLG TAD I RAMCEK ISZ RAMCEK DCA RSRBOT TAD I RAMCEK ISZ RAMCEK DCA RSRBOT+1 /RAM SOURCE BOT TAD I RAMCEK ISZ RAMCEK DCA RSRTOP TAD I RAMCEK ISZ RAMCEK DCA RSRTOP+1 /RAM SOURCE TOP TAD I RAMCEK ISZ RAMCEK DCA RSRLOW /PDP8 DESTINATION LOW TAD I RAMCEK ISZ RAMCEK AND N0003 RAL CLL RTL TAD RMDEH1 /PDP8 DESTINATION HIGH DCA RMCDF5 TAD I RAMCEK CDF 20 ISZ RAMCEK DCA RAMTEM /SUBROUTINE FUER ERROR TAD FRMPDP LOAD FORMAT SET PDP8WL PDP8CF PDP8WR STROBE CHEKLP, TAD RSRBOT LOAD LOW MEMADR TAD RSRBOT+1 LOAD HIGH MEMADR READ LOW MEMDAT MQL READ HIGH MEMDAT DST RMDAT /MEMDATEN IN TESTER MEMORY CAM RMCDF5, 0 TAD I RSRLOW CDF 20 AND N377 MQL ISZ RSRLOW CLA /TAD I RSRLOW FUER 16 BIT NOP /ISZ RSRLOW FUER 16 BIT NOP /AND N377 FUER 16 BIT DST PDP8DA /MEMDATEN IN PDP8 CAM DAD RMDAT DCM DAD PDP8DA DPSZ JMP RMERR RMDO, CAM DAD RSRBOT DCM DAD RSRTOP DPSZ SKP JMP CEKEND ISZ RSRBOT CLA TAD RSRBOT AND (400 SNA CLA JMP .+3 ISZ RSRBOT+1 DCA RSRBOT JMP CHEKLP CEKEND, TAD FRMHPR LOAD FORMAT CLEAR PDP8WL RETIN3, HLT JMP I RAMCEK RSRTOP, 0;0 N6203C, 6203 RSRLOW, 0 RMDEH1, 6201 RSRBOT, 0;0 RMFLG, 0 PAGE RMERR, CLA TAD RMFLG SZA CLA JMP .+2 JMS I RAMTEM SKP NULSUB, 0 CAM DAD RSRBOT TOCT16 TDC 4240 4257 240 DAD RMDAT TOCT16 TDC 4240 4257 240 DAD PDP8DA TOCT16 LINE CLA IAC DCA RMFLG JMP RMDO PDP8DA, 0;0 RMDAT, 0;0 RMTEMI, RAMTEM RAMTEM, 0 PAGE /CALL RAMFIL EINSCHREIBEN EINER KONSTANTEN IN TESTER-MEMORY /1. ARGUMENT: KONSTANTE LOW 8 BIT /2. ARGUMENT: KONSTANTE HIGH 8 BIT RMFLSR, 0 CLA TAD RMSIZ1 DCA RFSIZE TAD I RMFLSR ISZ RMFLSR MQL TAD I RMFLSR ISZ RMFLSR DST RAMSET CAM DST RMADR /ERSTE ADRESSE=0;LETZTE ADRESSE RMSIZE CLA TAD FRMPDP LOAD FORMAT SET PDP8WL PDP8CF PDP8WR STROBE RAMFLP, CAM DAD RMADR LOAD MEMADR DAD RAMSET LOAD MEMDAT NPULSE PDP8WR DAD RMADR DCM DAD RFSIZE, 0 DPSZ SKP JMP RMFEND ISZ RMADR CLA TAD RMADR AND (400 SNA CLA JMP .+3 ISZ RMADR+1 DCA RMADR JMP RAMFLP TAD FRMPDP LOAD FORMAT CLEAR PDP8WL RMFEND, JMP I RMFLSR RMADR, 0;0 RAMSET, 0;0 RMSIZ1, RMSIZE RMSIZE, 377;1 /8 BIT LOW, 8 BIT HIGH, MAX 16 BIT /CALL SRTOCT AUSGABE VON 16 BIT /INPUT HIGH IN AC, INPUT LOW IN MQ STOC16, 0 MOSTSR AND N377 DCA TTEM8 TAD TTEM8 AND N17 BSW CLL RTL DCA TTEM4 MQA AND N377 TAD TTEM4 MQL TAD TTEM8 RTR RTR AND N17 DCA TTEM4 TAD MN5 DCA TCTR5 TAD TTEM4 RAR RTR AND N1 TAD NP260 TCHAR CLA TAD TTEM4 NEXTC, AND N7 TAD NP260 TCHAR SHL 3 ISZ TCTR5 JMP NEXTC JMP I STOC16 N1, 1 N17, 17 N7, 7 MN5, -5 TCTR5, 0 TTEM8, 0 TTEM4, 0 NP260, 260 PAGE /CALL RMTSTS /TESTEN DES TESTER MEMORY MIT CHECKERBOARD UND INVERTIERTEM CHECKERBOARD RMTSTS, 0 CAM TAD RMCHBR DCA RMTEBR TAD RMSIZ2 DCA RLSIZE TAD RMSIZ2 DCA RRSIZE DCA RTFLG RMSTRT, CAM DST RMTADR CLA TAD FRMPDP LOAD FORMAT SET PDP8WL PDP8CF PDP8WR STROBE RLLOP, CAM DAD /ERSTE ADRESSE=0, LETZTE ADRESSE=RMZISE RMTADR LOAD MEMADR TAD RMTEBR LOAD LOW MEMDAT CLA /TAD RMTEBR FUER 16 BIT LOAD HIGH MEMDAT NPULSE PDP8WR CAM DAD RMTADR DCM DAD RLSIZE, 0 DPSZ SKP CLA JMP RMTRED ISZ RMTADR TAD RMTADR AND (400 SNA CLA JMP .+3 ISZ RMTADR+1 DCA RMTADR JMP RLLOP RMTRED, SET PDP8WL PDP8CF PDP8WR STROBE CAM DST RMTADR RRLOP, CAM DAD RMTADR LOAD MEMADR READ LOW MEMDAT MQL READ HIGH MEMDAT DST RTDATA /MEMDATA IN TESTER-MEMORY CAM TAD RMTEBR MQL CLA /TAD RMTEBR FUER 16 BITS DCM DAD RTDATA DPSZ JMP RTERR RTDO, CAM DAD RMTADR DCM DAD RRSIZE, 0 DPSZ SKP CLA JMP RNTEST ISZ RMTADR TAD RMTADR AND (400 SNA CLA JMP .+3 ISZ RMTADR+1 DCA RMTADR JMP RRLOP RNTEST, TAD RTFLG SNA CLA JMP RCHANG TAD FRMPDP LOAD FORMAT CLEAR PDP8WL JMP I RMTSTS RCHANG, TAD RMTEBR CMA AND N377 DCA RMTEBR CLA IAC DCA RTFLG JMP RMSTRT RTERR, CAM DAD RMTADR TOCT16 TDC 257 DAD RTDATA TOCT16 TDC 257 TAD RMTEBR MQL CLA /TAD RMTEBR FUER 16 BITS TOCT16 LINE JMP RTDO RMTADR, 0;0 RMTEBR, 0 RMCHBR, 252 RMSIZ2, RMSIZE RTFLG, 0 RTDATA, 0;0 PAGE /CALL SRCLR, STEUERSIGNALE =0 /1. ARGUMENT: STEUERSIGNALE SRCLR, 0 CLA TAD I SRCLR 6516 ISZ SRCLR CLA JMP I SRCLR /CALL SRSET, STEUERSIGNALE = 1 /1. ARGUMENT: STEUERSIGNALE SRSET, 0 CLA TAD I SRSET 6515 ISZ SRSET CLA JMP I SRSET /CALL SRPULN, STEUERSIGNALE =0,1 /1. ARGUMENT: STEUERSIGNALE SRPULN, 0 CLA TAD I SRPULN 6516 6515 ISZ SRPULN CLA JMP I SRPULN /CALL SRPULP, STEUERISGNALE =1,0 /1. ARGUMENT: STEUERSIGNALE SRPULP, 0 CLA TAD I SRPULP 6515 NOP NOP 6516 ISZ SRPULP CLA JMP I SRPULP /CALL SRPDPI, AUSLESEN AUS TESTER-MEMORY IN PDP8 /INPUT IN AC SRINPT, 0 6514 AND N377 JMP I SRINPT /CALL SRPDOT, AUSLESEN AUS PDP8 IN TESTER-MEMORY /OUTPUT IN AC SROUT, 0 6505 CMA 6506 NPULSE STROBE JMP I SROUT /CALL SRLOAD /1. ARGUMENT: INPUTSELECTOR A,B,C,D /400=HIGH NACH HIGH XXX /200=LOW, NACH LOW XXX /000=LOW,HIGH, NACH LOW,HIGH XXX /XXX= MEMADR, MEMDAT,PDPDAT,FORMAT,CLOCK SRLOAD, 0 AND N377 DCA SRTEM TAD I SRLOAD AND NLOW SZA CLA JMP SRLDLO TAD I SRLOAD AND NHIGH SZA CLA JMP SRLDHG TAD SRTEM SWP AND N377 DCA SRTEM SRLDLO, TAD I SRLOAD AND N7000 TAD SRTEM OUTPUT /LOW TAD I SRLOAD AND NLOW SZA CLA JMP SRLDED MQA DCA SRTEM SRLDHG, TAD I SRLOAD AND N7000 TAD NHIGH TAD SRTEM OUTPUT /HIGH SRLDED, ISZ SRLOAD CAM JMP I SRLOAD /CALL SRREAD /1. ARGUMENT: OUTPUTSELECTOR RA,RB,RC /400=HIGH, NACH HIGH XXX /200=LOW , NACH LOW XXX /000=LOW,HIGH, NACH /XXX= DEVADR, MEMDAT,DATOUT,STATUS SRREAD, 0 CLEAR SELECT TAD I SRREAD AND N3000 DCA SELARG SET SELARG, 0 CLA TAD I SRREAD AND NHIGH SZA CLA JMP SRREHG INPUT /LOW DCA SRTEM TAD I SRREAD AND NLOW SZA CLA JMP SRREED TAD SRTEM MQL SRREHG, SET HIGH INPUT /HIGH DCA SRTEM SRREED, TAD SRTEM ISZ SRREAD JMP I SRREAD SRTEM, 0 NLOW, LOW NHIGH, HIGH N377, 377 N3000, 3000 N7000, 7000 /CALL INIT SRINIT, 0 CLA TAD SPEED LOAD CLOCK SET STROBE PDP8WR CLEAR PDP8CF PDP8WL INTRPT HOLD RESET TAD FMT808 LOAD FORMAT TAD FMT808 DCA FRMHPR JMP I SRINIT SPEED, 370 FMT808, 127