"LATCH MA TO PREVENT BAD READS???" "****" "PROPERTY Atmel {open_collector=bk_cycle,bk_in_prog,md_dir};" module front Title 'front' Declarations dummy1 PIN; dummy2 PIN; clk7d5 PIN; " 7.5 MHz clock " " Parallel Port Inputs " host_clk PIN; " Receive clock (Strobe) " host_ack PIN; " Receive command data (h=data), or ack for rev " " transfers (Auto linefeed) " !rev_req PIN; " Request reverse transfer (initialize)" ecp_mode PIN; " In ECP mode (select printer)" " Parallel Port Outputs " periph_clk PIN istype 'reg_t,buffer'; " Transmit clock (Ack)" periph_ack PIN istype 'reg_t,buffer'; " Receive ack, or command!data for" "reverse transfers (h = data) " " (Busy) " !ack_rev PIN istype 'reg_t,buffer'; " Reverse transfer ok (Paper out)" !periph_req PIN istype 'com,buffer'; " Have reverse data (Error) " xflag PIN istype 'com,buffer'; " Will use ECP mode (Select) " " Parallel Port bidir data " pdata7..pdata0 PIN istype 'com,buffer'; " Data bits " pdata = [pdata7..pdata0]; " Parallel port state info " host_clk_d1 NODE istype 'reg,buffer'; " (Either host_clk or !host_ack) host_clk_d2 NODE istype 'reg,buffer'; host_clk_cnt1..host_clk_cnt0 NODE istype 'reg_t,buffer'; host_clk_cnt = [host_clk_cnt1..host_clk_cnt0]; byte_cnt1..byte_cnt0 NODE istype 'reg_t,buffer'; byte_cnt = [byte_cnt1..byte_cnt0]; reg_num2..reg_num0 NODE istype 'reg,buffer'; reg_num = [reg_num2..reg_num0]; our_addr PIN istype 'reg_t,buffer'; rev_req_sync PIN istype 'reg,buffer'; rev_req_cnt1..rev_req_cnt0 PIN istype 'reg_t,buffer'; rev_req_cnt = [rev_req_cnt1..rev_req_cnt0]; par_rx_rising NODE istype 'reg,buffer'; data_mode NODE istype 'reg,buffer'; " Switches " sw_halt NODE istype 'reg_t,buffer'; " halt switch " sw_step NODE istype 'reg_t,buffer'; " single step switch " sw_rotary2..sw_rotary0 NODE istype 'reg,buffer'; " Rotary switch state " sw_rotary = [sw_rotary2..sw_rotary0]; sw_momentary2..sw_momentary0 NODE istype 'reg,buffer'; " Rotary switch state " sw_momentary = [sw_momentary2..sw_momentary0]; [sw_data0..sw_data11] NODE istype 'reg,buffer'; " Switch register " sw_data = [sw_data0..sw_data11]; " Pin not needed " sw_sw PIN istype 'reg_t,buffer'; " Switch switch " [dbk_data0..dbk_data11] NODE istype 'reg,buffer'; " Switch register " dbk_data = [dbk_data0..dbk_data11]; sw_start NODE istype 'reg_t,buffer'; " True in momentary switch cycle in progress " " I/O " omni_data0..omni_data11 PIN istype 'buffer'; " Omnibus data lines " omni_data = [omni_data0..omni_data11]; !omni_data_out PIN istype 'buffer'; !omni_data_in PIN istype 'buffer'; ma0..ma11 PIN istype 'reg,buffer'; " Omnibus address lines " ma = [ma0..ma11]; !ma_in PIN istype 'buffer'; ema0..ema2 PIN istype 'reg,buffer'; " Omnibus extended address lines " ema = [ema0..ema2]; " Inputs " !initialize PIN; " Reset pin input " run PIN; " Run state " !tp1 PIN; " Time pulse 1 " !tp2 PIN; " Time pulse 2 " !tp3 PIN; " Time pulse 3 " !tp4 PIN; " Time pulse 4 " ts1 PIN; " Time state 1 " ts2 PIN; " Time state 2 " ts3 PIN; " Time state 3 " ts4 PIN; " Time state 3 " !fset PIN; " Fetch state " !user_mode PIN; " User mode signal " md0..md11 PIN; " MD bus " md = [md0..md11]; !omni_f PIN; " F signal " !omni_d PIN; " D signal " !omni_e PIN; " E signal " !ir0 PIN; " IR0 signal " !ir1 PIN; " IR1 signal " !ir2 PIN; " IR2 signal " !md_dir PIN istype 'reg,buffer'; " md_dir signal " pause PIN; " pause signal " " Outputs " bk_in_prog PIN istype 'com,buffer'; " break in progress signal " bk_cycle PIN istype 'com,buffer'; " break cycle " init_out PIN; " Drive initialize " stop PIN; " Stop " mem_start PIN; " Start memory cycle " !ind1 PIN; " Indicator select 1 " !ind2 PIN; " Indicator select 2 " load_addr PIN; " Load address enable " load_addr_en PIN; " Load address enable " key_cntrl PIN; " More load address stuff " ms_ir_dis PIN; " Data break " bk_data_cont PIN; " Inc during data break " mem_start_reg NODE istype 'reg,buffer'; " Start memory cycle internal " " Testing " test_reg7..test_reg0 PIN istype 'reg,buffer'; test_reg = [test_reg7..test_reg0]; " For our databreak " "in" !int_strobe PIN; "out" ma_ms_load PIN istype 'reg,buffer'; cpma_disable PIN; break_prio PIN; need_break NODE istype 'reg,buffer'; need_break_sync NODE istype 'reg,buffer'; our_break_del NODE istype 'reg,buffer'; break_done NODE istype 'reg,buffer'; read_break_pending NODE istype 'reg,buffer'; write_break_pending NODE istype 'reg,buffer'; bk_active NODE istype 'reg,buffer'; !our_break PIN istype 'reg,buffer'; "Also external MA enable, out when low" sw_cycle NODE istype 'reg,buffer'; " Switch cycle active " [latch_led11..latch_led0] NODE istype 'reg,buffer'; " Latched led display " latch_led = [latch_led11..latch_led0]; sw_any NODE istype 'com,buffer'; " Any switch active " data_disp NODE istype 'com,buffer'; " Load data into display " sr_to_data NODE istype 'com,buffer,keep'; " Drive SR onto data " sr_read NODE istype 'com,buffer'; " Read SR instruction " led_clk_clk NODE istype 'com,buffer'; " Clock for status leds " led_clk NODE istype 'reg,buffer'; " Clock for status leds " sw_start_d1 NODE istype 'reg,buffer'; " Switch start delay 1 " "sw_start_d2 NODE istype 'reg,buffer'; Switch start delay 2 " "load_byte_0, load_byte_1, load_byte_2, load_byte_3 NODE istype 'com,buffer,keep';" [delay_cnt2..delay_cnt0] NODE istype 'reg,buffer'; " Timing delays " delay_cnt = [delay_cnt2..delay_cnt0]; sw_pulse NODE istype 'reg_t,buffer'; " Switch action pulse " ma_inc NODE istype 'reg,buffer'; "[disk_addr11..disk_addr0] NODE istype 'reg,buffer';" "disk_addr = [disk_addr11..disk_addr0];" our_addr_bits = (!pdata6 & !pdata5 & pdata4 & !pdata3); cmd_mode = (!host_ack & ecp_mode & !ack_rev); rx_byte_0 = (!byte_cnt1 & !byte_cnt0); rx_byte_1 = (!byte_cnt1 & byte_cnt0); rx_byte_2 = ( byte_cnt1 & !byte_cnt0); rx_byte_3 = ( byte_cnt1 & byte_cnt0); "Convienence" load_byte_0 = (data_mode & !ack_rev & par_rx_rising & rx_byte_0); load_byte_1 = (data_mode & !ack_rev & par_rx_rising & rx_byte_1); load_byte_2 = (data_mode & !ack_rev & par_rx_rising & rx_byte_2); load_byte_3 = (data_mode & !ack_rev & par_rx_rising & rx_byte_3); "xilinx property 'INIT=S relay7 relay6 relay5 relay4 relay3 relay2 relay1 relay0';" " Map switches to rotary switch = 0 to 5 " sw_none = (!sw_rotary2 & !sw_rotary1 & !sw_rotary0); sw_bus = (!sw_rotary2 & !sw_rotary1 & sw_rotary0); sw_mq = (!sw_rotary2 & sw_rotary1 & !sw_rotary0); sw_md = (!sw_rotary2 & sw_rotary1 & sw_rotary0); sw_ac = ( sw_rotary2 & !sw_rotary1 & !sw_rotary0); sw_status = ( sw_rotary2 & !sw_rotary1 & sw_rotary0); sw_state = ( sw_rotary2 & sw_rotary1 & !sw_rotary0); " = Map switches to momentary switch = 1 to 6, all 0s = no switch " sw_none2 = (!sw_momentary2 & !sw_momentary1 & !sw_momentary0); sw_addr_load = (!sw_momentary2 & !sw_momentary1 & sw_momentary0); sw_exd_addr = (!sw_momentary2 & sw_momentary1 & !sw_momentary0); sw_clear = (!sw_momentary2 & sw_momentary1 & sw_momentary0); sw_cont = ( sw_momentary2 & !sw_momentary1 & !sw_momentary0); sw_exam = ( sw_momentary2 & !sw_momentary1 & sw_momentary0); sw_dep = ( sw_momentary2 & sw_momentary1 & !sw_momentary0); write_sw_reg = (our_addr & !reg_num2 & !reg_num1 & reg_num0); write_ma = (our_addr & !reg_num2 & reg_num1 & reg_num0); write_break = (our_addr & reg_num2 & reg_num1 & !reg_num0); write_test = (our_addr & reg_num2 & reg_num1 & reg_num0); " Dont forget to update read_any" read_break = (our_addr & !reg_num2 & reg_num1 & !reg_num0); read_disk_addr = (our_addr & !reg_num2 & reg_num1 & reg_num0); read_leds = (our_addr & reg_num2 & !reg_num1 & !reg_num0); read_test = (our_addr & reg_num2 & reg_num1 & reg_num0); read_any = (read_break # read_disk_addr # read_leds # read_test); COUNT = (sw_start_d1 & !(delay_cnt0 & delay_cnt1 & delay_cnt2)); " Should these exist? " led_state_sel = sw_state; led_md_sel = sw_md; led_data_sel = data_disp; Equations "load_byte_0 = (data_mode & !ack_rev & par_rx_rising & rx_byte_0);" "load_byte_1 = (data_mode & !ack_rev & par_rx_rising & rx_byte_1);" "load_byte_2 = (data_mode & !ack_rev & par_rx_rising & rx_byte_2);" "load_byte_3 = (data_mode & !ack_rev & par_rx_rising & rx_byte_3);" " <> par_rx_rising.clk = clk7d5; par_rx_rising := (host_clk_cnt1 & host_clk_cnt0 & periph_ack & host_clk_d1 & !host_clk_d2); data_mode.clk = clk7d5; data_mode := ecp_mode & our_addr & (!ack_rev & host_ack # ack_rev & periph_ack); " Parallel port interface " xflag = ecp_mode; " Clean up either host clock or host ack. Invert host ack so it will have " " the same idle state as host clock. " host_clk_d1.clk = clk7d5; host_clk_d1 := host_clk & !ack_rev # !host_ack & ack_rev # (!our_addr & !cmd_mode); host_clk_d2.clk = clk7d5; host_clk_d2 := host_clk_d1; host_clk_cnt.clk = clk7d5; host_clk_cnt0.t = !(host_clk_d1 $ host_clk_d2) & !(host_clk_cnt1 & host_clk_cnt0) # (host_clk_d1 $ host_clk_d2) & host_clk_cnt0; host_clk_cnt1.t = !(host_clk_d1 $ host_clk_d2) & host_clk_cnt0 & !(host_clk_cnt1 & host_clk_cnt0) # (host_clk_d1 $ host_clk_d2) & host_clk_cnt1; " Force high when not our addr, in data mode each acks for self " periph_ack.clk = clk7d5; periph_ack.t = !periph_ack & (!ack_rev & host_clk_cnt1 & host_clk_cnt0 & !host_clk_d2 & (our_addr & (!write_break # write_break & !write_break_pending) # !host_ack & our_addr_bits) # ack_rev) # periph_ack & our_addr & (!ack_rev & host_clk_cnt1 & host_clk_cnt0 & host_clk_d2 # ack_rev & !rev_req_cnt1 & !rev_req_cnt0) # !periph_ack & !our_addr; periph_clk.clk = clk7d5; periph_clk.t = !periph_clk & (ack_rev & !host_clk_d2 & host_clk_cnt1 & host_clk_cnt0 # !ack_rev) # periph_clk & (ack_rev & host_clk_d2 & host_clk_cnt1 & host_clk_cnt0 & (!read_break # (read_break & read_break_pending # write_break & !our_break_del)) ); byte_cnt.clk = clk7d5; " Reset to 0 when command cycle, increment on each rising edge of host clk " byte_cnt0.t = !data_mode & byte_cnt0 # par_rx_rising & data_mode; byte_cnt1.t = !data_mode & byte_cnt1 # par_rx_rising & byte_cnt0 & data_mode; " Transmit stuff " rev_req_sync.clk = clk7d5; rev_req_sync := rev_req; rev_req_cnt.clk = clk7d5; rev_req_cnt0.t = rev_req_sync & !(rev_req_cnt1 & rev_req_cnt0) # !rev_req_sync & !(!rev_req_cnt1 & !rev_req_cnt0); rev_req_cnt1.t = rev_req_sync & rev_req_cnt0 & !(rev_req_cnt1 & rev_req_cnt0) # !rev_req_sync & !rev_req_cnt0 & !(!rev_req_cnt1 & !rev_req_cnt0); dummy1 = latch_led11; dummy2 = led_clk; " IO Needed for fitter to pick pin #'s " pdata.oe = ack_rev; //pdata = input_data & (byte_cnt == 0); //when byte_cnt == 0 then // pdata = relay.pin //else when byte_cnt == 1 then // pdata = ^h55; //pdata7 = read_leds & (latch_led4 & rx_byte_0 # run & rx_byte_1); //pdata6 = read_leds & latch_led5 & rx_byte_0; //pdata5 = read_leds & latch_led6 & rx_byte_0; //pdata4 = read_leds & latch_led7 & rx_byte_0; //pdata3 = read_leds & (latch_led8 & rx_byte_0 # latch_led0 & rx_byte_1); //pdata2 = read_leds & (latch_led9 & rx_byte_0 # latch_led1 & rx_byte_1); //pdata1 = read_leds & (latch_led10 & rx_byte_0 # latch_led2 & rx_byte_1); //pdata0 = read_leds & (latch_led11 & rx_byte_0 # latch_led3 & rx_byte_1); when read_leds & rx_byte_0 then pdata = [run,0,0,0,latch_led0..latch_led3]; else when read_leds & rx_byte_1 then pdata = [latch_led4..latch_led11]; else when read_leds & rx_byte_2 then pdata = [0,ema0.pin,ema1.pin,ema2.pin,ma0.pin,ma1.pin,ma2.pin,ma3.pin]; else when read_leds & rx_byte_3 then pdata = [ma4..ma11].pin; else when read_break & !byte_cnt0 then // Send this lsb first pdata = [dbk_data4..dbk_data11]; else when read_break & byte_cnt0 then pdata = [0,0,0,0,dbk_data0..dbk_data3]; else when read_test then pdata = test_reg; "else when read_disk_addr & !byte_cnt0 then " " pdata = [0,0,0,0,disk_addr0..disk_addr3];" "else when read_disk_addr & byte_cnt1 then" " pdata = [disk_addr4..disk_addr11];" ack_rev.clk = clk7d5; ack_rev.t = !ack_rev & (our_addr & read_any & rev_req_cnt1 & rev_req_cnt0) # ack_rev & (!rev_req_cnt1 & !rev_req_cnt0); periph_req = 0; our_addr.clk = clk7d5; our_addr.t = !our_addr & (cmd_mode & par_rx_rising & our_addr_bits) # our_addr & (!ack_rev & cmd_mode & par_rx_rising & !our_addr_bits); " Load register # on rising edge of clock in command mode " reg_num.clk = clk7d5; reg_num := [pdata2..pdata0] & cmd_mode & par_rx_rising # reg_num & !(cmd_mode & par_rx_rising); "This may cause bus contention on turnaround" omni_data_in = !omni_data_out & !(sr_to_data # our_break.fb & write_break & ts2); omni_data_out = sr_to_data # our_break.fb & write_break & ts2; omni_data.oe = omni_data_out; omni_data = sw_data; test_reg.clk = clk7d5; when (load_byte_0 & write_test) then test_reg := pdata else test_reg := test_reg; "0..11 msb to lsb" sw_data.clk = clk7d5; sw_data := [pdata3..pdata0,sw_data4..sw_data11] & (load_byte_1 & write_sw_reg # (load_byte_1 # load_byte_3) & write_break) # [sw_data0..sw_data3,pdata7..pdata0] & (load_byte_0 & write_sw_reg # (load_byte_0 # load_byte_2) & write_break) # sw_data & !((load_byte_1 # load_byte_0) & write_sw_reg # (load_byte_0 # load_byte_1 # load_byte_2 # load_byte_3) & write_break); sw_sw.clk = clk7d5; sw_sw.t = !sw_sw & (pdata4 & load_byte_1 & write_sw_reg) # sw_sw & (!pdata4 & load_byte_1 & write_sw_reg); sw_step.clk = clk7d5; sw_step.t = !sw_step & (pdata5 & load_byte_1 & write_sw_reg) # sw_step & (!pdata5 & load_byte_1 & write_sw_reg); sw_halt.clk = clk7d5; sw_halt.t = !sw_halt & (pdata6 & load_byte_1 & write_sw_reg) # sw_halt & (!pdata6 & load_byte_1 & write_sw_reg); sw_start.clk = clk7d5; sw_start.t = !sw_start & (pdata6 & data_mode & par_rx_rising & write_sw_reg & rx_byte_2) # sw_start & (!pdata6 & data_mode & par_rx_rising & write_sw_reg & rx_byte_2); sw_rotary.clk = clk7d5; sw_rotary := [pdata2..pdata0] & load_byte_2 & write_sw_reg # sw_rotary & !(load_byte_2 & write_sw_reg); sw_momentary.clk = clk7d5; sw_momentary := [pdata5..pdata3] & load_byte_2 & write_sw_reg # sw_momentary & !(load_byte_2 & write_sw_reg); ma.clk = clk7d5; ma.oe = our_break.fb; ma_in = read_leds & (rx_byte_1 # rx_byte_2 # rx_byte_3) & ack_rev; [ma0..ma11] := [ma0.fb,ma1.fb,ma2.fb,ma3.fb,pdata7..pdata0] & !ma_inc & load_byte_0 & write_ma # [pdata3..pdata0,ma4.fb,ma5.fb,ma6.fb,ma7.fb,ma8.fb,ma9.fb, ma10.fb,ma11.fb] & !ma_inc & load_byte_1 & write_ma # [ma0..ma11].fb & !ma_inc & !((load_byte_1 # load_byte_0) & write_ma) # ([ma0..ma11].fb + 1) & ma_inc; ema.clk = clk7d5; ema.oe = our_break.fb; [ema0..ema2] := [pdata6..pdata4] & load_byte_1 & write_ma # [ema0..ema2].fb & !(load_byte_1 & write_ma); ind1 = !(sw_bus # sw_ac) & !load_addr_en; ind2 = !(sw_mq # sw_ac) & !load_addr_en # load_addr_en; stop = sw_halt & fset # sw_step; sw_any = sw_addr_load # sw_exd_addr # sw_clear # sw_cont # sw_exam # sw_dep; sw_start_d1.clk = clk7d5; sw_start_d1 := sw_start & sw_any; "sw_start_d2.clk = clk7d5;" "sw_start_d2 := sw_start_d1;" delay_cnt.clk = clk7d5; delay_cnt := (delay_cnt + 1) & COUNT # delay_cnt & sw_start_d1 & !COUNT; " Set at 3, clear at 6" sw_pulse.clk = clk7d5; sw_pulse.aclr = !(ts1 & !run); sw_pulse.t = delay_cnt2 & delay_cnt1 & !delay_cnt0 # !delay_cnt2 & delay_cnt1 & delay_cnt0 # sw_pulse & !sw_start_d1; "sw_cycle.clk = sw_start_d1;" sw_cycle.clk = sw_start_d1; sw_cycle.aclr = !sw_start; sw_cycle := !run & ts1 & sw_any; data_disp = ts1 & (sw_mq # sw_ac # sw_status) # sw_bus; mem_start = sw_pulse & mem_start_reg; mem_start_reg := (sw_dep # sw_exam # sw_cont); mem_start_reg.aclr = tp4 # initialize; mem_start_reg.clk = sw_pulse; sr_read = ts3 & !user_mode & omni_f & md0 & md1 & md2 & md3 & md9 & !md11; " ARE WE DRIVING TOO LONG DURING MA LOAD?" sr_to_data = sw_dep & mem_start_reg & ts2 # (sw_exd_addr # sw_addr_load) & sw_cycle # sr_read; init_out = sw_pulse & sw_clear; load_addr = sw_pulse & (sw_exd_addr # sw_addr_load); key_cntrl = sw_cycle & (sw_dep # sw_exam # sw_exd_addr); ms_ir_dis = sw_cycle & (sw_dep # sw_exam # sw_exd_addr # sw_addr_load) # our_break.fb; load_addr_en = sw_cycle & (sw_exd_addr # sw_addr_load); bk_data_cont = sw_cycle & (sw_exam); "Probably should be tp2 but not routed to xilinx" led_clk_clk = tp1 & !sw_bus # ts3 & sw_bus; led_clk.clk = led_clk_clk; " prevent update while reading leds" led_clk := (sw_mq # sw_ac # sw_status) # read_leds & ack_rev; led_clk.aclr = (tp4 & !(read_leds & ack_rev)) # initialize; " Low is transparent " latch_led.le = led_clk; latch_led11 := omni_data11.pin & led_data_sel # md11 & led_md_sel # bk_cycle.pin & led_state_sel; latch_led10 := omni_data10.pin & led_data_sel # md10 & led_md_sel # bk_in_prog & led_state_sel; latch_led9 := omni_data9.pin & led_data_sel # md9 & led_md_sel # pause & led_state_sel; latch_led8 := omni_data8.pin & led_data_sel # md8 & led_md_sel # sw_sw & led_state_sel; latch_led7 := omni_data7.pin & led_data_sel # md7 & led_md_sel # bk_data_cont & led_state_sel; latch_led6 := omni_data6.pin & led_data_sel # md6 & led_md_sel # md_dir.pin & led_state_sel; latch_led5 := omni_data5.pin & led_data_sel # md5 & led_md_sel # ir2 & led_state_sel; latch_led4 := omni_data4.pin & led_data_sel # md4 & led_md_sel # ir1 & led_state_sel; latch_led3 := omni_data3.pin & led_data_sel # md3 & led_md_sel # ir0 & led_state_sel; latch_led2 := omni_data2.pin & led_data_sel # md2 & led_md_sel # omni_e & led_state_sel; latch_led1 := omni_data1.pin & led_data_sel # md1 & led_md_sel # omni_d & led_state_sel; latch_led0 := omni_data0.pin & led_data_sel # md0 & led_md_sel # omni_f & led_state_sel; bk_active.clk = int_strobe; bk_active := need_break_sync; bk_active.aclr = tp1 # initialize; our_break.clk = tp4; our_break.aclr = initialize; our_break := bk_active & (!omni_data0.pin & !omni_data1.pin & !omni_data2); need_break_sync.clk = int_strobe; need_break_sync := need_break; need_break_sync.aclr = initialize # our_break; need_break.clk = clk7d5; need_break.aclr = tp1 & our_break.fb; need_break := (read_break & ack_rev & !read_break_pending & !our_break_del) # write_break & (load_byte_1 # load_byte_3) # need_break; read_break_pending.clk = clk7d5; read_break_pending := break_done & our_break_del # read_break_pending & !(par_rx_rising & byte_cnt0) & ack_rev; // read_break_pending & !(load_byte_1 # load_byte_3) & ack_rev; write_break_pending.clk = clk7d5; write_break_pending := write_break & (load_byte_1 # load_byte_3) # write_break_pending & !break_done & ecp_mode; cpma_disable = bk_active; bk_in_prog = bk_active; break_prio.oe = bk_active & ts4; break_prio = 1; bk_cycle = our_break.fb; " ms_ir_dis set above " md_dir.clk = tp1; md_dir.aset = initialize; md_dir := !(our_break.fb & read_break); dbk_data.clk = tp3; dbk_data := md & our_break.fb # dbk_data & !our_break.fb; our_break_del.clk = clk7d5; our_break_del := our_break # our_break_del & !break_done; break_done.clk = clk7d5; break_done := our_break_del & !our_break; ma_inc.clk = clk7d5; ma_inc := break_done & our_break_del; ma_ms_load.clk = tp1; ma_ms_load := our_break.fb; ma_ms_load.aclr = initialize; "disk_addr.clk = tp3;" "when [md3..md11] == ^o743 & pause then" " disk_addr := omni_data;" "else" " disk_addr := disk_addr;" end front