v host_clk_cnt host_clk_cnt[1:0]_q v byte_cnt byte_cnt[1:0]_q v reg_num reg_num[2:0]_q v pdata pdata[7:0] v relay relay[7:0]_q v input_data input_data[7:0] watch clk7d5 host_clk host_ack rev_req periph_clk periph_ack ack_rev watch ecp_mode periph_req watch host_clk_cnt watch pdata byte_cnt reg_num our_addr_q watch par_rx_rising_q data_mode_q watch relay step 50ns clock clk7d5 0 1 high ecp_mode high host_clk low host_ack high rev_req assign input_data 35\h c 3 | Address power control, addr 1, reg 4 low host_clk assign pdata c\h c 6 h host_clk c 12 | Read data l rev_req c 3 release pdata c 5 h host_ack c 8 l host_ack c 8 h host_ack c 8 l host_ack c 4 | back to write, send addr 1, reg 1 h rev_req c 6 assign pdata 9\h c 2 l host_clk l host_ack c 6 h host_clk c 6 | Now send relay data h host_ack c 6 h host_clk c 6 l host_clk assign pdata aa\h c 6 h host_clk c 6