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[MEMT1   1|12|71
[MEMORY TEST 1
[INTERIM MEMS
$1
JMP 1A
$20
[PRESET ON
#1A CLR
OPR 10
[PRESET OFF
LDA i
3
OPR 10
STA i
#9O   [OUT VECTOR
[READ KEY
#1B KST
JMP p-1
KBD i
SHD i
"L;
JMP 1L [LOAD ADDR
SHD i
"E;
JMP 1E [EXAM
SHD i
"F;
JMP 1F [FILL
SHD i
"S;
JMP 1S [STEP ADDR
SHD i
1200 [EOL
JMP 3B [LAP6
JMP 1B
[LOAD ADDR
#1L LSW
STA i
#8A
RSW
STA i
#9A
JMP 2D [DISP ADDR
JMP 1B
[EXAM
#1E JMP 2A [OUT ADDR
LDA [READ
9O
BCO i
4000
JMP 3A [OUT CHK
CLR [IN DATA
OPR 0
JMP 1B
[FILL
#1F JMP 2A [OUT ADDR
RSW [DATA OUT
OPR 6
LDA [WRITE
9O
BCO i
2000
JMP 3A [OUT CHK
JMP 1B
[STEP ADDR
#1S JMP 2D [DISP ADDR
JMP 1B
[
[SUBRS
[DISP ADDR
#2D LDA
8A
ATR
LDA
9A
JMP 0
[
[OUT ADDR
#2A LDA
8A
OPR 4
LDA
9A
OPR 7
JMP 0
[
[MMSUBRS  1|12|71
[
[CONTROL OUT AND CHK
#3A OPR 10
STC 9O
OPR 11
[FIX NO RET FROM PRESET AND DATA PRO
BSE i
3
SAE
9O
HLT [NO RET
JMP 0
[
[TO LAP6
#3B SET i 15
RCG
SET i 16
7300
JMP 15
[
[CONTROL OUT
#3C OPR 10
STC 9O
JMP 0
[
[TEST CONTROL RET
[p+1 IF NOT RET
[p+2 [IF RET
#3D CLR
OPR 11
SAE
9O
JMP 0 [NOT RET
XSK i 0 [RET
JMP 0
[