This is the G104D sense inhibit board from the MM8-E 4kx12 core memory option. This board was used to read the contents of a word via the 12 sense lines and to set the bits needed in a word to 0 by using the sense lines to inhibit flipping the core. More core information. The addressing of the core (1.5M) was done by the G104 sense inhibit board (1.3M)
The white bar at the top center covers the pulse transformers used to drive the transistors driving the sense/inhibit line. The jumpers in the lower right select the extended memory address for the board. The rotary switch in the upper right adjusts the sense timing to reliably sense the memory contents. The wire in the upper left is from an ECO (engineering change order) to the board (fixes a design error). Back view of board (1.6M)
Feel free to contact me, David Gesswein email@example.com with any questions, comments on the web site, or if you have related equipment, documentation, software etc. you are willing to part with. I am interested in anything PDP-8 related, computers, peripherals used with them, DEC or third party, or documentation.
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